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ASAHI KASEI
[AK4525]
AK4525
20Bit Stereo ADC & DAC with X' tal Osc
GENERAL DESCRIPTION The AK4525 has a dynamic range of 100dB and is well-suited middle-range MD, surround system, musical instruments and car audio. Analog inputs are full-differential with single-end capability. Analog outputs are single-ended. The AK4525 has X' tal oscillation circuit and master mode. FEATURES o Stereo ADC - 64x Oversampling - Sample Rate Ranging from 32kHz to 48kHz - S/(N+D): 92dB - Dynamic range, S/N: 100dB - Digital HPF for offset cancellation o Stereo DAC - 128x Oversampling - Sampling Rate Ranging from 32kHz to 48kHz - 2nd order SCF + 2nd order CTF - Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling - S/(N+D): 90dB - Dynamic Range, S/N: 100dB - Soft Mute o High Jitter Tolerance o Master Clock: 256fs, 384fs, 512fs o X' tal Oscillation circuit o Master/Slave Mode o Analog Power Supply: 4.5 to 5.5V, Digital Power Supply: 3.1 to 5.5V
VA AINL+ AINLAINR+ AINRVREFH VCOM Common Voltage LPF Modulator Modulator PDN 8x Interpolator AGND VD DGND Decimation Filter CMODE Clock Gen & Divider MCKO XTI XTO LRCK HPF SCLK Serial I/O Interface SDTO SDTI DIF0 DIF1 SMUTE M/S
Modulator Modulator
HPF
Decimation Filter
AOUTL
AOUTR
LPF
8x Interpolator
DEM0 DEM1
MS0053-E-00 -1-
2000/9
ASAHI KASEI
[AK4525]
n Ordering Guide
AK4525VF AKD4525 -40 +85C 28pin VSOP (0.65mm pitch) Evaluation Board for AK4525
n Pin Layout
VREFH AINR+ AINRAINL+ AINLVA AGND XTI XTO DIF0 DIF1 LRCK SCLK SDTI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 VCOM AOUTR AOUTL CMODE PDN DGND VD MCKO M/S (Internal Pull-down) TST DEM1 DEM0 SMUTE SDTO
AK4525
24 23
Top View
22 21 20 19 18 17 16 15
n Difference with AK4522 and AK4523
AK4522 Not available Not available 2.7 5.5V -10 70C 24pin VSOP AK4523 Not available Not available 3.0 5.5V -40 85C 28pin VSOP AK4525 Available Available 3.1 5.5V -40 85C 28pin VSOP
Crystal Oscillator Master Mode Digital Power Supply Ambient Operating Package
MS0053-E-00 -2-
2000/9
ASAHI KASEI
[AK4525]
PIN/FUNCTION
No. 1 Pin Name VREFH I/O I Function Positive Voltage Reference Input Pin, VA Used as a positive voltage reference by ADC & DAC. VREFH should be connected externally to filtered VA. Rch Analog Positive Input Pin Rch Analog Negative Input Pin Lch Analog Positive Input Pin Lch Analog Negative Input Pin Analog Power Supply Pin Analog Ground Pin X'tal Input Pin X'tal Output Pin Audio Data Interface Format 0 Pin Audio Data Interface Format 1 Pin Input/Output Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Audio Serial Data Output Pin Soft Mute Pin When this pin goes "H", soft mute cycle is initiated. When returning "L", the output mute releases. De-emphasis Frequency Select 0 Pin De-emphasis Frequency Select 1 Pin Test Pin This pin must be connected to DGND. Master/Slave Mode (Internal pull-down pin) "H": Master mode, "L": Slave mode Master Clock Output Pin Digital Power Supply Pin Digital Ground Pin Power-Down Mode Pin Master Clock Select Pin (Internal biased pin) "H": 384fs, "L": 256fs, "NC": 512fs Lch Analog Output Pin Rch Analog Output Pin Common Voltage Output Pin, VA/2
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AINR+ AINRAINL+ AINLVA AGND XTI XTO DIF0 DIF1 LRCK SCLK SDTI SDTO SMUTE
I I I I I O I I I/O I/O I O I
17 18 19 20 21 22 23 24 25 26 27 28
DEM0 DEM1 TST M/S MCKO VD DGND PDN CMODE AOUTL AOUTR VCOM
I I I I O I I O O O
Note: All input pins except pull-down or biased pins should not be left floating.
MS0053-E-00 -3-
2000/9
ASAHI KASEI
[AK4525]
ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V; Note 1) Parameter Symbol min Power Supplies Analog VA -0.3 Digital VD -0.3 |AGND-DGND| (Note 2) GND Input Current, Any Pin Except Supplies IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65
Notes: 1. All voltages with respect to ground. 2. AGND and DGND must be same voltage.
max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 85 150
Units V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND=0V; Note 1) Parameter Symbol min typ Power Supplies Analog VA 4.5 5.0 (Note 3) Digital VD 3.1 5.0
Notes: 1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical.
max 5.5 VA
Units V V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0053-E-00 -4-
2000/9
ASAHI KASEI
[AK4525]
ANALOG CHARACTERISTICS (Ta=25C; VA, VD=5.0V; AGND=DGND=0V; VREFH=VA; fs=44.1kHz; SCLK=64fs; Signal Frequency =1kHz; 20bit Data; Measurement frequency = 10Hz 20kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Differential Inputs; Analog Source Impedance=470 Resolution 20 Bits S/(N+D) (-0.5dB Input) (Note 4) 84 92 dB DR (-60dB Input, A-Weighted) (Note 5) 94 100 dB S/N (A-Weighted) (Note 5, 6) 94 100 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.1 0.3 dB Gain Drift 20 ppm/C Input Voltage (AIN=0.6 x VREFH) (Note 7) 2.85 3.0 3.15 Vpp Input Resistance 15 25 k Power Supply Rejection (Note 8) 50 dB DAC Analog Output Characteristics: Resolution 20 Bits S/(N+D) 80 90 dB DR (-60dB Output, A-Weighted) (Note 5) 94 100 dB S/N (A-Weighted) (Note 6, 9) 94 100 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/C Output Voltage (AOUT=0.58 x VREFH) 2.65 2.9 3.15 Vpp Load Resistance 5 k Load Capacitance 25 pF Power Supply Rejection (Note 8) 50 dB Power Supplies VA=VD=5V Analog, VA PDN= "H" 40 55 mA Digital, VD PDN= "H" 12 20 mA Power Down PDN= "L" (Note 10) 6 12 mA
Notes: 4. In case of single ended input, S/(N+D)=80dB(typ, @VA=5V). 5. In case of 16bit, DR and S/N of ADC are 98dB. DR of DAC is 98dB. 6. S/N measured by CCIR-ARM is 96dB at each converter and 94dB at ADC to DAC loopback. 7. Full scale input for each AIN+/- pin is 1.5Vpp in differential mode. 8. PSR is applied to VA, VD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 9. As the input data is "0", S/N is 100dB regardless of resolution. 10. X'tal circuit is oscillating and all digital input pins are held VD or DGND.
MS0053-E-00 -5-
2000/9
ASAHI KASEI
[AK4525]
FILTER CHARACTERISTICS (Ta=25C; VA=4.5 5.5V; VD=3.1 5.5V; DEM0= "1", DEM1= "0") Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband (Note 11) -0.005dB PB 0 -0.02dB 0 -0.06dB 0 -6.0dB 0 Stopband SB 24.34 Passband Ripple PR Stopband Attenuation SA 80 Group Delay (Note 12) GD Group Delay Distortion GD ADC Digital Filter (HPF): Frequency Response (Note 11) -3dB FR -0.5dB -0.1dB DAC Digital Filter: Passband (Note 11) -0.06dB PB 0 -6.0dB 0 Stopband SB 24.1 Passband Ripple PR Stopband Attenuation SA 43 Group Delay (Note 12) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 20.0kHz
typ
max 19.76 20.02 20.20 22.05 0.005
Units kHz kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz
29.3 0 0.9 2.7 6.0 20.0 22.05 0.06 14.7 0.2 -
kHz kHz kHz dB dB 1/fs dB
Notes: 11. The passband and stopband frequencies scale with fs. For example, 20.02kHz at -0.02dB is 0.454 x fs. The reference frequency of these responses is 1kHz. 12. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 20bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20bit data of both channels on input register to the output of analog signal.
DC CHARACTERISTICS (Ta=25C; VA=4.5 5.5V; VD=3.1 5.5V) Parameter Symbol min High-Level Input Voltage (Except CMODE pin) VIH 70%VD Low-Level Input Voltage (Except CMODE pin) VIL High-Level Input Voltage (CMODE pin) VIH 95%VD Low-Level Input Voltage (CMODE pin) VIL Hight-Level Output Voltage (Iout=-80A) VOH VD-0.4 Low-Level Output Voltage (Iout=80A) VOL Input Leakage Current (Note 14) Iin -
typ -
Max 30%VD 10%VD 0.4 10
Units V V V V V V A
Notes: 14. CMODE pin has internal pull-up and pull-down devices, nominally 50kohm. M/S pin has internal pull-down device, nominally 46kohm.
MS0053-E-00 -6-
2000/9
ASAHI KASEI
[AK4525]
SWITCHING CHARACTERISTICS (Ta=25C; VA=4.5 5.5V; VD=3.1 5.5V; CL=20pF) Parameter Symbol min Master Clock Timing 256fs 8.192 384fs 12.288 512fs 16.384 MCKO Output Frequency fMCK 8.192 Duty Cycle dMCK Rise Time (Note 15) tR Fall time (Note 15) tF LRCK Timing Frequency fs 32 Duty Cycle dfs 45 Serial Interface Timing Slave mode SCLK Period tSCK 320 SCLK Pulse Width Low tSCKL 65 Pulse Width High tSCKH 65 tLRS 45 LRCK Edge to SCLK "" (Note 16) tSLR 45 SCLK "" to LRCK Edge (Note 16) tLRM LRCK to SDTO (MSB) tSSD SCLK "" to SDTO tSDH 40 SDTI Hold Time tSDS 25 SDTI Setup Time Master mode SCLK Frequency fSCK SCLK Duty dSCK tMSLR -20 SCLK "" to LRCK tSSD SCLK "" to SDTO tSDH 40 SDTI Hold Time tSDS 25 SDTI Setup Time Reset Timing PDN Pulse Width (Note 17) tPD 150 tPDV PDN "" to SDTO valid (Note 18)
typ
max 12.288 18.432 24.576 24.576
Units MHz MHz MHz MHz % ns ns kHz %
50 5 5 48 55
40 70
ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns ns 1/fs
64fs 50 20 70
516
Notes: 15. VD=3.1V, 0.8 2.0V. 16. SCLK rising edge must not occur at the same time as LRCK edge. 17. The AK4525 can be reset by bringing PDN "L". When the state of CMODE changes during operation, the AK4525 should be reset by PDN. PDN should be held "L" for 5ms to allow the X'tal oscillation to begin at power-up. 18. These cycles are the number of LRCK rising from PDN rising.
MS0053-E-00 -7-
2000/9
ASAHI KASEI
[AK4525]
n Timing Diagram
LRCK tSLR tLRS tSLKL tSLKH
50%VD
SCLK
50%VD
tLRM
tSSD
SDTO tSDH tSDS SDTI
50%VD
50%VD
Serial Interface Timing (Slave mode)
LRCK
50%VD
tMSLR SCLK 50%VD
tSSD 50%VD
SDTO tSDS
tSDH 50%VD
SDTI
Serial Interface Timing (Master mode)
tPD 70%VD PDN tPDV SDTO 30%VD
Reset & Initialize Timing
MS0053-E-00 -8-
2000/9
ASAHI KASEI
[AK4525]
OPERATION OVERVIEW n System Clock
The master clock (MCLK) can be a crystal resonator placed across the XTI and XTO pin. The relationship between the MCLK and the desired sample rate is defined in Table 1. The MCLK frequency is set by CMODE pin and the sampling rate corresponds to 32kHz 48kHz. In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon power-up. All external clocks must be present unless PDN= "L", otherwise excessive current may result from abnormal operation of internal dynamic logic. MCLK 384fs CMODE= "H" 12.2880MHz 16.9344MHz 18.4320MHz SCLK 512fs CMODE= "NC" 16.3840MHz 22.5792MHz 24.5760MHz 64fs 2.0480MHz 2.8224MHz 3.0720MHz
fs 32.0kHz 44.1kHz 48.0kHz
256fs CMODE= "L" 8.1920MHz 11.2896MHz 12.2880MHz
Table 1. System Clock Example at normal speed When the state of CMODE changes under operation, the AK4525 should be reset by PDN. At that case, the analog outputs should be muted externally because some click noise may occur. XTI AK4525
XTO
Figure 1. X'tal resonator connection External loading capacitor ( 22pF to AGND for XTI/XTO) are required for a crystal oscillator. PDN should be held "L" for 5ms to allow the X'tal oscillation to begin at power-up.
MS0053-E-00 -9-
2000/9
ASAHI KASEI
[AK4525]
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The AK4525 supports the master mode. In this case, SCLK and LRCK are outputs and the frequency of SCLK is fixed to 64fs. Four serial data modes selected by the DIF0 and DIF1 pins are supported as shown in Table 3. In all modes the serial data has MSB first, 2's compliment format. The data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least significant bits will be truncated. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO (ADC) 20bit, MSB justified 20bit, MSB justified 20bit, MSB justified IIS (I2S) SDTI (DAC) 16bit, LSB justified 20bit, LSB justified 20bit, MSB justified IIS (I2S) L/R H/L H/L H/L L/H SCLK (Slave) 32fs 40fs 40fs 32fs or 40fs
Table 2. Serial Data Modes Note: In master mode, SCLK frequency is fixed to 64fs.
LRCK(i)
0 1 2 3 9 10 11 12 13 14 15 0 1 2 9 10 11 12 13 14 15 0 1
SCLK(i:32fs) SDTO(o) SDTI(i)
0
19 18 17
11 10
9
8
7
6
5
4
19 18 17
11 10
9
8
7
6
5
4
19
15 14 13
1 2 3
7
17
6
18
5
19
4
20
3
2
30
1
31
0
0
15 14 13
1 2 3
7
17
6
18
5
19
4
20
3
2
1
31
0
0
15
1
SCLK(i:64fs) SDTO(o) SDTI(i)
19 18 17 3 2 1 0 19 18 17 3 2 1 0 19
Don't Care
15 14 13
12 11
2
1
0
Don't Care
15 14 13 12 11
2
1
0
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB Lch Data
Rch Data
Figure 2. Mode 0 Timing LRCK(i)
0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1
SCLK(i:64fs) SDTO(o) SDTI(i)
19 18 8 7 6 0 19 18 8 7 6 0 19
Don't Care 19:MSB, 0:LSB
19 18
12 11
1
0
Don't Care
19 18
12 11
1
0
Lch Data
Rch Data
Figure 3. Mode 1 Timing
MS0053-E-00 - 10 -
2000/9
ASAHI KASEI
[AK4525]
LRCK(i)
0 1 2 17 18 19 20 21 0 1 2 17 18 19 20 21 0 1
SCLK(i:64fs) SDTO(o) SDTI(i)
19 18 3 2 1 0 19 18 3 2 1 0 19
19 18
3
2
1
0
Don't Care
23 22
3
2
1
0
Don't Care
19
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 2 Timing LRCK(i)
0 1 2 3 9 10 11 12 13 14 15 0 1 2 9 10 11 12 13 14 15 0 1
SCLK(i:32fs) SDTO(o) SDTI(i)
0
4
1
19 18
2 3
12 11 10
17 18 19
9
20
8
21
7
6
31
5
0
4
1
19 18
2 3
12 11
17 18
10
19
9
20
8
21
7
6
31
5
0
4
1
SCLK(i:64fs) SDTO(o) SDTI(i)
19 18 4 3 2 1 0 19 18 4 3 2 1 0
19 18
4
3
2
1
0
Don't Care
19 18
4
3
2
1
0
Don't Care
19:MSB, 0:LSB Lch Data Rch Data
Figure 5. Mode 3 Timing
n Digital High Pass Filter
The ADC of AK4525 has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and also scales with sampling rate (fs).
MS0053-E-00 - 11 -
2000/9
ASAHI KASEI
[AK4525]
n De-emphasis Filter
The DAC of AK4525 includes the digital de-emphasis filter (tc=50/15s) by IIR filter. This filter corresponds to three frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled for input audio data. The de-emphasis is also disabled at DEM0= "1" and DEM1= "0". DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz
Table 3. De-emphasis filter control
n Soft Mute Operation
Soft mute operation is performed at digital domain. When SMUTE goes to "H", the output signal is attenuated by - during 1024 LRCK cycles. When SMUTE is returned to "L", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE 1024/fs (1) 1024/fs (3)
0dB Attenuation
-
GD (2) GD
Noise level
-100dB
Notes: (1) The output signal is attenuated by - during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. Figure 6. Soft Mute Operation
MS0053-E-00 - 12 -
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ASAHI KASEI
[AK4525]
n Power-Down & Reset
The ADC and DAC of AK4525 are placed in the power-down mode by bringing a power down pin, PDN "L" and each digital filter is also reset at the same time.This reset should always be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 7 shows the power-up sequence.
PDN
516/fs (1)
ADC Internal State DAC Internal State
Normal Operation
Power-down
Init Cycle
Normal Operation
Normal Operation GD (2)
Power-down
Normal Operation GD
ADC In (Analog) ADC Out (Digital) DAC In (Digital)
(2) GD (3) "0"data (4)
"0"data GD (5) (5)
DAC Out (Analog) Clock In
MCLK,LRCK,SCLK
The clocks may be stopped.
External Mute
(6)
Mute ON
(1) The analog part of ADC is initialized after exiting the power-down state. (2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (3) ADC output is "0" data at the power-down state. (4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. (5) Click noise occurs at the edge of PDN. (6) Please mute the analog output externally if the click noise (5) influences system application. Figure 7. Power-up Sequence During the power-down mode, the crystal oscillator is left running. The condition of the outputs are as follows. SDTO = "L" MCKO = Clock out LRCK = "H" (master mode) SCLK = "L" (master mode) AOUT = VCOM (VA/2)
MS0053-E-00 - 13 -
2000/9
ASAHI KASEI
[AK4525]
SYSTEM DESIGN
Figure 8 shows the system connection diagrams. This is an example which analog signal is input by single ended circuit. In case of differential input, please refer to Figure 11. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
4.5 5.5V Analog Supply
10u + 0.1u 1 2.2n 470 4.7u 2.2n 4.7u + 0.1u + 0.1u 7 8 9 AGND XTI XTO DIF0 DIF1 LRCK SCLK SDTI 2 0.1u 3 4 5 6 VREFH AINR+ AINRAINL+ AINLVA VCOM AOUTR AOUTL CMODE PDN DGND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.1u + 10u 5 0.1u + 10u 470
3.1 5.5V Digital Supply
AK4525
VD MCKO M/S TST DEM1 DEM0 SMUTE SDTO
Format Setting
10 11 12 13
Mode Setting
Audio Controller
14
Figure 8. Typical Connection Diagram
Digital Ground
Analog Ground
1 2 3 4 5 VREFH AINR+ AINRAINL+ AINLVA AGND XTI XTO DIF0 DIF1 LRCK SCLK SDTI VCOM AOUTR AOUTL CMODE PDN DGND 28 27 26 25 24 23 22 21 20 19 18 17 16 15
System Controller
6 7 8 9 10 11 12 13 14
AK4525
VD MCKO M/S TST DEM1 DEM0 SMUTE SDTO
Figure 9. Ground Layout
MS0053-E-00 - 14 -
2000/9
ASAHI KASEI
[AK4525]
5V analog
5V digital
VA
VD AK4525 Case 1. 5V system
VD System Controller
5V analog
3.3V digital
VA
VD AK4525
VD System Controller
Case 2. 5V/3.3V system Figure 10. Power Supply Arrangement
1. Grounding and Power Supply Decoupling The AK4525 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK4525 should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4525 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The differential voltage between VREFH and AGND sets the analog input/output range. VREFH pin is normally connected to VA with a 0.1F ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4525. 3. Analog Inputs The ADC inputs are differential and internally biased to the common voltage (VA/2) with 25k (typ) resistance. Figure 7 is a circuit example which analog signal is input by single end. The signal can be input from either positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. In case of single ended input, the distortion around full scale degrades compared with differential input. Figure 11 is a circuit example which analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x VREFH Vpp. The AK4525 can accept input voltages from AGND to VA. The ADC output data format is 2's complement. The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below a negative fill scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by the internal HPF. The AK4525 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs.
MS0053-E-00 - 15 -
2000/9
ASAHI KASEI
[AK4525]
4.7k 1.5Vpp 10k 330 330 AINR3 1.5Vpp AINL+ 4 AINL5 4.7k Vop=VA=5V 4.7k Same circuit 0.1u BIAS + 10u + NJM2100 10k Vop + 10k Vop 22u Signal 3.2Vpp
AK4525
AINR+ 2
1.5nF
Figure 11. Differential Input Buffer Example 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.58 x VREFH Vpp. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). The internal switched-capacitor filter and continuous-time filter remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. Figure 12 shows the example of external op-amp circuit with 6dB gain. The output signal is inverted by using the circuit in this case.
27u AOUTL 2.9Vpp + Vop 4.7k BIAS 10u + 0.1u 4.7k Rch Op-amp Optional amp with 6dB gain Vop + 10u + NJM5532 27k Lch Out 5.22Vpp 10k 18k Vop=12V
Figure 12. External analog circuit example (gain=6dB)
MS0053-E-00 - 16 -
2000/9
ASAHI KASEI
[AK4525]
PACKAGE
28pin VSOP (Unit: mm)
*9.80.2 0.675 28 15 A 7.60.2 +0.1 0.220.1 0.65 0.15-0.05 0.10.1 Detail A 0.50.2 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10 2000/9 - 17 1.250.2
1
14
n Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
MS0053-E-00
*5.60.2
ASAHI KASEI
[AK4525]
MARKING
AKM AK4525VF XXXBYYYYC
XXXBYYYYC XXXB : YYYYC :
Date code identifier
Lot number (X : Digit number, B : Alpha character) Assembly date (Y : Digit number, C Alpha character)
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0053-E-00 - 18 -
2000/9

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